In a junction field effect transistor, a reverse bias voltage is applied from a gate electrode to a pn junction provided at the side of a channel region through which carriers pass so that a depletion layer extending from the pn junction spreads to the channel region. Thus, the conductance of the channel region is controlled and a switching operation is performed.
Among such junction field effect transistors, there is a lateral field effect transistor, in which carriers in the channel region move parallel to the surface of the device. Here, as an exemplary lateral field effect transistor, a lateral field effect transistor disclosed in Japanese Patent Laying-Open No. 2003-68762 is described.
As shown in FIG. 11, on an SiC single crystal substrate 101, a p− type semiconductor layer 102 is formed. On p− type semiconductor layer 102, an n type semiconductor layer 103 is formed. On n type semiconductor layer 103, a p type semiconductor layer 110 is formed.
In p type semiconductor layer 110, an n+ type source region layer 104, a p+ type gate region layer 106 and an n+ type drain region layer 105 are formed separated by a prescribed distance from one another.
On n+ type source region layer 104, p+ type gate region layer 106 and n+ type drain region layer 105, a source electrode 107, a gate electrode 109 and a drain electrode 108 are formed, respectively.
On the other hand, the above-described conventional lateral field effect transistor involves the following problem. In a state where the field effect transistor is off, when a positive voltage is applied to drain region layer 105 through drain electrode 108, as shown in FIG. 11, depletion layer 121 extends between drain region layer 105 and gate region layer 106, as well as from the interface between p− type semiconductor layer 102 and n type semiconductor layer 103 positioned immediately below drain region layer 105 toward the interface between SiC single crystal substrate 101 and p− type semiconductor layer 102.
Here, as shown in FIG. 11, crystal defects 120 exist in relatively large numbers at the interface between SiC single crystal substrate 101 and p− type semiconductor layer 102. Therefore, the dielectric breakdown voltage in this portion is lower than that in a region that is fully separated from the region containing many crystal defects.
As a result, a problem is invited that the dielectric breakdown easily occurs when an edge of depletion layer 121 reaches near SiC single crystal substrate 101.